Field Programmable Gate Arrays (FPGAs) are more flexible than Application-Specific Integrated Circuits (ASICs) at the cost of 20× bigger area, 4× longer delay, and 12× higher power consumption approximately [1]. The drawbacks of FPGAs lie in the expensive routing architecture, which accounts for about 70% of the area, 80% of the delay and 60% of the power of the whole chip [2]. Power consumption is a serious barrier for the distribution of FPGAs in a large set of consumer applications. Prior art publications [3]-[5] demonstrate low-power FPGA designs where a low supply voltage is employed to save up to 50% of the power consumption. However, low-power FPGAs generally suffer from large delay degradation (up to 2×).
Resistive Memories (RMs) [6], a member of Non-Volatile Memory (NVM) family [7], open opportunities in advancing the FPGA technology with high density, instant power-on and excellent energy efficiency. Overwhelming Static Random Access Memories (SRAMs) intrinsically, RMs hold storage when powered down and consume less leakage power. Besides, RMs can be fabricated between the Back-End-Of-Line (BEOL) metal lines, moving the configuration memories onto the top of the transistors, thereby improving the integration density. Using RMs as standalone memories, FPGAs can benefit a ˜50% power reduction from instant power-on and normal power-off, compared to SRAM-based counterparts [8]. Furthermore, RMs motivate the exploration of novel FPGA architectures whose routing structures are directly employing RMs in the data path. In the novel architectures, RMs play the role of both configurable memories and programmable switches. Previous works [9]-[12] demonstrate significant improvements in area, delay and power. The BEOL integration leads to area-savings and the Low-Resistance State (LRS) of RMs (down to 75% lower on-resistance than pass transistors) reduces the delay of critical path. Finally, a power efficiency comes from zero leakage power in sleep mode.